The present invention relates to the field of electronics and, more particularly, to a method and apparatus for multiplying clock rates.
High speed integrated circuits are available currently that operate at very high clock rates. A common method for producing these high clock rates involves multiplying a readily available lower speed clock signal to achieve the desired clock rate. Two well known techniques for multiplying clock signals involve using either conventional flip-flop multipliers or analog phase locked loop (PLL) multipliers.
Conventional flip-flop multipliers utilize an analog control system that incorporates resistors and capacitors. In this type of multiplier, the desired output signal, e.g., a high speed clock signal having a precise clock rate and a 50% duty cycle, is dependent on the values of the resistors and capacitors. Since high clock rates are involved, the resistor and capacitor values must be precise to achieve the desired output signal, thereby increasing component costs. In addition, resistor and capacitor values vary with environmental conditions, such as ambient temperature, thus making it difficult to maintain their precise values.
Analog PLL multipliers utilize analog components to control clock rates. These analog components are sensitive to temperature and supply voltages, which can affect the delay and slew rate of signals produced by analog PLL multipliers. In addition, integrated circuits containing analog components require a large amount of semiconductor surface area and are difficult to redesign for use with newer fabrication technologies, e.g., redesigning an analog PLL multiplier designed for fabrication using 0.2 xcexcm fabrication technologies to be produced using 0.13 xcexcm fabrication technologies is a very difficult and time consuming task.
Accordingly, there is a need for clock rate multiplier methods and apparatus that are not subject to the limitations associated with conventional flip-flop multipliers and analog PLL multipliers. The present invention fulfills this needs among others.
The present invention is a digital clock rate multiplier that overcomes the aforementioned problems through the use of digital circuitry, which is resistant to variation in environmental conditions and well suited for use in integrated circuits. The digital clock rate multiplier multiplies the clock rate of an input signal to produce an output signal having a higher clock rate than the input signal. The digital clock rate multiplier includes a digital delay signal generator for developing first and second delay signals based on the input signal and a delayed version of the input signal, and a clock circuit for producing the output signal based at least partially on the first and second delay signals.
The digital delay signal generator develops a delayed output signal from an input signal for use in developing the first and second delay signals. Preferably, the delayed output signal is created by producing a plurality of delayed version of the input signal, enabling a counter for a predetermined period of the input signal, counting specified edges (e.g., rising edges) of the delayed version of the input signal when the counter is enabled, and selecting one of the delayed versions as the delayed output signal based on the number of edges counted.
One aspect of the present invention is a method for multiplying an input signal. The method includes digitally generating a first delay signal and a second delay signal based on the input signal, generating a first clock signal based on the first delay signal, generating a second clock signal based on the second delay signal, and combining the first and second clock signals to produce a multiplied output signal.
Another aspect of the invention is a digital multiplier for multiplying an input signal. The digital multiplier includes a digital delay signal generator for generating a first delay signal and a second delay signal based on the input signal, and a clock circuit for producing a multiplied output signal based at least partially on the first and second delay signals.
Another aspect of the invention is a digital delay circuit for delaying an input signal. The digital delay circuit includes one or more delay elements for delaying the input signal; a first multiplexer for receiving the input signal as delayed by each of the delay elements; a second multiplexer for receiving at least a portion of the input signals as delayed by each of the delay elements; a counter enabled during a first period of the input signal for controlling the first multiplexer and for counting specified edges of delayed versions of the input signal passed by the first multiplexer; and a divider coupled between the counter and the second multiplexer for dividing the count signal, thereby configuring the second multiplexer to pass the input signal delayed by a second period of the input signal to produce a delayed clock signal.
Another aspect of the invention is a method for delaying an input signal. The method includes producing a plurality of delayed versions of the input signal, enabling a counter for a period of the input signal, counting specified edges of the plurality of delayed version when the counter is enabled, and selecting a delayed output signal from the plurality of delayed versions based on the number of specified edges counted.